SMTA Silicon Valley (San Jose) Chapter and SMCBA (Surface Mount and Circuit Board Association) Meeting

Technical Meeting on Solder Joint Voiding Reduction during Refolw and Panel Discussion


Tuesday, September 19th 2023 (Americas)

17:00 – 19.00 PST (US)

Wednesday, September 20th 2023 (Asia)

10:00 – 12:00 AEST (Australia)

08:00 – 10:00 SST (Singapore)


SMCBA members will be provided the Zoom link upon RSVP.

 ‍To verify your membership status and/or RSVP for this event, please contact:

ANTHONY AT This email address is being protected from spambots. You need JavaScript enabled to view it. OR

TEAGAN AT This email address is being protected from spambots. You need JavaScript enabled to view it.


Non-members may book through the SMTA San Jose Chapter using the following link:

Cost $30 USD


Technical Presentations from:

Tony Lentz, Field Application and R & D Engineer, FCT Solder, USA

Title: Voiding in Solder Joints from a Solder Paste Perspective

Abstract: Voiding in solder joints is an ongoing concern for printed circuit board assembly (PCBA) manufacturers and original equipment manufacturers (OEMs).  Voiding can lead to electrical circuit interference, thermal dissipation issues, and potential mechanical weakness in the solder joint.  As ball grid arrays (BGAs) and bottom terminated components (BTCs) become increasingly popular, the potential for voiding in solder joints has increased.  One major concern with voids in solder joints is the difficulty of rework.  It can be challenging to reduce voiding through traditional rework processes.  Voiding limits are often imposed on PCBA manufacturers for specific components.  These voiding concerns lead electronics manufacturers to find ways to minimize voiding potential.  Solder paste and the print and reflow processes can have a large influence on voiding in solder joints.  Changes to the solder paste and print and reflow processes are relatively easy and are often the first step in efforts to reduce voiding.  This presentation explores the influence of solder paste flux, solder alloy, solder powder size, stencil design, and reflow profile on voiding in solder joints.  Void data from prior work will be presented, and recommendations made to minimize voiding potential.

Biography: Tony Lentz began working in the electronics industry in 1994. He entered the industry as a process engineer at a circuit board manufacturer. Since 1999, Tony has worked for FCT Companies as a chemical laboratory manager, production facility manager, and most recently a field application engineer.  Since 2013, Tony has focused on field application and R&D for FCT Assembly solder and stencil products.  He has extensive experience doing research and development, quality control, and technical service with products used to manufacture and assemble printed circuit boards.  He has written and presented many papers at industry events.  Tony is the chair of the IPC J-STD-004 (Flux) standard task group and vice-chair of the IPC J-STD-005 (Solder Paste) standard task group.  He is a speaker of distinction with SMTA and holds BS. and MS. degrees in Chemistry.

Jasbir Bath, Owner, Bath Consultancy LLC, USA

Title: A review of efforts in the Industry to Reduce Voiding in Solder Joints in Relation to Development Work and Standardization

Abstract: Voiding in solder joints has been a concern for many years in relation to electrical/ thermal and solder joint reliability. Initial standards to set limits on solder joint voiding were focused on BGA components and lately has concentrated on BTCs (Bottom Termination Components). The presentation will review efforts to reduce voiding in solder joints from a stencil aperture reduction perspective during solder paste printing, to paste development to reflow profile development in terms of preheat and reflow temperatures and times. It will also discuss the effect of component and board solderability on voiding and review developments of standards in this area.

Biography: Jasbir has over 30 years of experience in research, design, development and implementation in the areas of soldering, surface mount and packaging technologies.  He began his engineering career as a technical officer at the International Tin Research Institute (ITRI) in the UK.  In 1998 he joined Flex/Solectron as a corporate lead engineer specializing in soldering materials, processes and components.  In 2008 he formed his own company providing process consulting and training services to the electronics manufacturing industry. He is a Consultant with Koki Solder Americas, Inc.. He is the co-chair of the INEMI Board Assembly Roadmap Chapter and is currently the Vice President of Technical Programs for the SMTA (Surface Mount Technology Association) Silicon Valley (San Jose) chapter. He is the recipient of the SMTA Excellence in Leadership Award and is the editor of 5 books on lead-free manufacturing and reliability. He has BS and MS degrees in Materials Science from the University of Manchester, England.

Thomas Tong, Process Technology Manager, BTU International, Singapore

Title: Reflow Void Reduction Strategies and Vacuum Reflow

Abstract: . Voiding occurs in almost all SMT reflow soldered component parts, with volatiles trapped at the edges of a solder paste deposit with the solder paste deposit melting and encapsulating the volatiles. Material flow and process adjustments are some necessary steps to alleviate the amount of void formation to an acceptable level. With the rise in the use of large Thermal Pads under components for heat dissipation and increased voiding occurring, vacuum reflow can help to reduce the amount of voids. The presentation will discuss the types and sources of voids, the strategies for void reduction and overview the vacuum reflow process.

Biography: Thomas Tong received a Bachelor of Technology degree in Manufacturing Technology from the National University of Singapore. He had 12 years of experience in various SMT process and engineering positions for companies such as Apple and 3Com. He was with Indium Corporation for 7 years both as a Technical Manager and Sales Manager in Asia, acquiring knowledge in soldering materials. Thomas has 15 years of experience in Process and Application of Thermal Processing Solutions with equipment manufacturers including Despatch and BTU. Thomas is with BTU as a Process Technology Manager, focusing on developing Thermal Processing Solutions for present and future needs in both the SMT and Semiconductor Packaging Industry.

Jose Servin, Automotive Electronics Technologist, Vitesco Technologies,  Mexico

Title: Types of Voids, New IPC Voiding Criteria for the Automotive Industry and the Influence of Reflow on Voids

Abstract: The presentation will discuss a classification as well as definitions for different void types in electronics assembly including process, design-induced and shrinkage voids in terms of which of them really have some influence on solder joint reliability and how the impact of the most known void type has little impact on reliability. A revision of the different criteria described in IPC A 610 – J -STD 001 automotive addendum and the origins of this revision will be presented.  The concept of solder coverage will be reviewed with a discussion of possible improvements in reflow to reduce voiding.

Biography: José-María Servín Olivares has worked in electronics assemblies for more than 19 years in SMT, BE, and electronics component manufacturing mainly as a Technologist. He has published several articles on soldering, and failure analysis. He holds MSc and Ph.D. degrees in soldering materials from the Autonomous University of the State of Morelos, Mexico. He is the leader of the reflow group at Vitesco, Mexico. He has also been an IPC member for more than 17 years in the development of the Electronics Assembly Norms. As a member of the IPC A-610 and J STD-001 working groups, in 2018 he became chairman of IPC A-610 and J STD-001 Automotive Addendums that complements the norms for the automotive industry.  His studies include crack analysis, material evaluations, new techniques for material analysis, voiding, and electronics contaminants. He has published several patents.